DI GUO

Associate Professor                                     Phone: +86-18202783120

Physics Department                                 Email: diguo@mail.ccnu.edu.cn

Central China Normal University

Wuhan, Hubei, P.R.China

EDUCATION

2008 B.Sc., Modern Physics, University of Science and Technology of China (USTC)

2015 Ph.D., Electronic Science and Technology, University of Science and Technology of China

2013-2015, exchange visiting scholar in Southern Methodist University

2015 ~2017 Postdoctoral Fellow, Physics Department, Southern Methodist University

My research mainly focuses on the high-speed data transmission implementation from chip level to system level, including high-speed VCSEL driving/PD receiving (TIA，LA) ASICs design, digital interface ASICs design, PLL/CDR, serializer/deserializer ASIC design,  high-speed PCB and interconnect (25Gbps+) simulation/design, encoder/decoder verification and implementation in FPGA and array optical transmitter module development.

2013~2015 • Principle investigator at SMU of a generic collider detector R&D project to develop a customized 120 Gbps radiation-tolerant array optical link to be deployed in generic collider detector data acquisition. As the first fully-customized array optical transmitter module in the high energy physics application, the progress of the project has been published in the 2013 and 2014 TWEPP, and invited as an oral presentation in 2014 TWEPP.

• Designed and tested a digital interface-encoding ASIC (640M clk). This ASIC receives 8-channel serial outputs (640Mbps/ch) from two ADCs, consists of FIFO, CRC generator, scrambler and frame builder, outputs 8-bit parallel data after encoding with three clock domains within the chip. The design adopts a full-custom method with optimization of hardware algorithms to push the data rate to the upper limit of the process.

2015~2017 • Designed and tested an ultra-low power 4 x 10+ Gbps VCSEL array driver in TSMC 65nm process at CERN for Versatile Link project, an international collaboration providing next-generation optical data links for CMS/ATLAS experiments at LHC. The novel output structure of this driving ASIC is now applied for a patent in the U.S.

• Designed a 12 x 10+ Gbps VCSEL array driver ASIC in Global Foundry 65nm process, in UTD under the collaboration of Vega Wave Systems, Inc., for potential commercialization possibility.

• Designed a versatile high-speed SLVS/LVDS driver/receiver IP block with pre-emphasis/equalizer in TSMC 65nm process at CERN for the lpGBTX project, the next-generation chipset implementing multipurpose high-speed bidirectional optical links for high-energy physics experiments.

• Designed and tested three VCSEL driving/PD receiving chips: 4 x 14-Gbps VCSEL driver, 4 x 25-Gbps VCSEL driver and 4 x 14-Gbps receiver (TIA+LA) in TSMC 65nm CMOS technology.